CDC925DLRG4

CDC925DLRG4
Mfr. #:
CDC925DLRG4
Descrizione:
IC 133-MHZ CLOCK SYNTH 56-SSOP
Ciclo vitale:
Nuovo da questo produttore.
Scheda dati:
CDC925DLRG4 Scheda dati
Consegna:
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ECAD Model:
Maggiori informazioni:
CDC925DLRG4 maggiori informazioni CDC925DLRG4 Product Details
Attributo del prodotto
Valore attributo
Produttore
Texas Instruments
categoria di prodotto
Orologio/Temporizzazione - Specifico dell'applicazione
Serie
-
Confezione
Tape & Reel (TR) Imballaggio alternativo
Pacchetto-Custodia
56-BSSOP (0.295", 7.50mm Width)
Temperatura di esercizio
0°C ~ 85°C
Tipo di montaggio
Montaggio superficiale
Tensione di alimentazione
2.375 V ~ 3.465 V
Pacchetto-dispositivo-fornitore
56-SSOP
PLL
Scopo principale
Server CPU Intel
Ingresso
Cristallo
Produzione
CMOS
Numero di circuiti
1
Rapporto ingresso: uscita
1899/12/30 1:24:00
Ingresso differenziale: uscita
No/No
Frequenza-Max
133MHz
Tags
CDC925D, CDC925, CDC92, CDC9, CDC
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC 133-MHZ CLOCK SYNTH 56-SSOP
***ark
IC, CLOCK SYNTHESIZER, 133MHZ, SSOP-56; Clock IC Type:Clock Synthesizer / Driver; Frequency:133MHz; No. of Outputs:19; Supply Current:12mA; Supply Voltage Range:3.135V to 3.465V, 2.375V to 2.625V; Digital IC Case Style:SSOP ;RoHS Compliant: Yes
***as Instruments
The CDC925 is a clock synthesizer/driver that generates system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100\. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN\ terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP\ or CPU_STOP\, the outputs operate normally. With a low-level applied to the PCI_STOP\ or CPU_STOP\ terminals, the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state. The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100\ control input. The PCI bus frequency is fixed to 33MHz. Since the CDC925 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.
Parte # Descrizione Azione Prezzo
CDC925DLRG4
DISTI # CDC925DLRG4-ND
IC 133-MHZ CLOCK SYNTH 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    CDC925DLRG4
    DISTI # N/A
    Clock Synthesizer / Jitter Cleaner 133-MHz Clock Synth/ Drvr0
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      Disponibilità
      Azione:
      Available
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      1000
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