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SN74S374DWRE4

SN74S374DWRE4
Mfr. #:
SN74S374DWRE4
Descrizione:
Flip Flops Octal D-Ty Positive Edge-Trig F-F
Ciclo vitale:
Nuovo da questo produttore.
Scheda dati:
SN74S374DWRE4 Scheda dati
Consegna:
DHL FedEx Ups TNT EMS
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ECAD Model:
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SN74S374DWRE4 maggiori informazioni SN74S374DWRE4 Product Details
Attributo del prodotto
Valore attributo
Produttore:
Texas Instruments
Categoria di prodotto:
Infradito
RoHS:
Y
Numero di circuiti:
8
Famiglia logica:
74S
Tipo di logica:
Fermo trasparente tipo D
Polarità:
Non invertente
Tipo di ingresso:
Parallelo
Tipo di uscita:
Single-ended
Tempo di ritardo di propagazione:
17 ns
Corrente di uscita ad alto livello:
- 6.5 mA
Corrente di uscita a basso livello:
20 mA
Tensione di alimentazione - Min:
4.75 V
Tensione di alimentazione - Max:
5.25 V
Temperatura di esercizio minima:
0 C
Temperatura massima di esercizio:
+ 70 C
Stile di montaggio:
SMD/SMT
Pacchetto/custodia:
SOIC-20
Confezione:
Bobina
Funzione:
Interfaccia bus di tipo D
Altezza:
2.35 mm
Lunghezza:
12.8 mm
Larghezza:
7.52 mm
Marca:
Texas Instruments
Numero di canali:
8
Numero di righe di input:
3
Numero di linee di uscita:
8
Tensione di alimentazione operativa:
4.75 V to 5.25 V
Tipologia di prodotto:
Infradito
Quantità confezione di fabbrica:
1
sottocategoria:
CI logici
Unità di peso:
0.028254 oz
Tags
SN74S374D, SN74S374, SN74S37, SN74S3, SN74S, SN74, SN7
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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 20SOIC
***as Instruments
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up. The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
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Disponibilità
Azione:
Available
Su ordine:
3500
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